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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a microprocessor supervisory circuits adm8690Cadm8695 features upgrade for adm690/adm695, max690Cmax695 specified over temperature low power consumption (0.7 mw) precision voltage monitor reset assertion down to 1 v v cc low switch on-resistance 0.7 v normal, 7 v in backup high current drive (100 ma) watchdog timer100 ms, 1.6 s, or adjustable 400 na standby current automatic battery backup power switching extremely fast gating of chip enable signals (3 ns) voltage monitor for power fail available in tssop package applications microprocessor systems computers controllers intelligent instruments automotive systems functional block diagrams adm8691 adm8693 adm8695 4.65v 1 reset and watchdog timebase reset generator watchdog transition detector watchdog timer 1.3v v out ce out low line reset reset watchdog output ( wdo ) power fail output ( pfo ) v batt v cc ce in osc in osc sel watchdog input (wdi) power fail input (pfi) batt on 1 voltage detector = 4.65v (adm8691, adm8695) 4.40v (adm8693) adm8690 adm8692 ADM8694 4.65v 1 v out reset power fail output ( pfo ) v batt v cc watchdog input (wdi) power fail input (pfi) 1 voltage detector = 4.65v (adm8690, ADM8694) 4.40v (adm8692) 2 reset pulse width = 50ms (ad8690, adm8692) 200ms (ADM8694) watchdog transition detector (1.6s) reset generator 2 1.3v one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 general description the adm8690Cadm8695 family of supervisory circuits offers complete single chip solutions for power supply monitoring and battery control functions in microprocessor systems. these functions include m p reset, backup battery switchover, watchdog timer, cmos ram write protection and power failure warning. the complete family provides a variety of configurations to sat- isfy most microprocessor system requirements. the adm8690, adm8692 and ADM8694 are available in 8-pin dip packages and provide: 1. power-on reset output during power-up, power-down and brownout conditions. the reset output remains opera- tional with v cc as low as 1 v. 2. battery backup switching for cmos ram, cmos microprocessor or other low power logic. 3. a reset pulse if the optional watchdog timer has not been toggled within a specified time. 4. a 1.3 v threshold detector for power fail warning, low bat tery detection or to monitor a power supply other than +5 v. the adm8691, adm8693 and adm8695 are available in 16-pin dip and small outline packages (including tssop) and provide three additional functions: 1. write protection of cmos ram or eeprom. 2. adjustable reset and watchdog timeout periods. 3. separate watchdog timeout, backup battery switchover, and low v cc status outputs. the adm8690Cadm8695 family is fabricated using an ad- vanced epitaxial cmos process combining low power con- sumption (0.7 mw), extremely fast chip enable gating (3 ns) and high reliability. reset assertion is guaranteed with v cc as low as 1 v. in addition, the power switching circuitry is de- signed for minimal voltage drop thereby permitting increased output current drive of up to 100 ma without the need of an external pass transistor.
adm8690Cadm8695Cspecifications parameter min typ max units test conditions/comments battery backup switching v cc operating voltage range adm8690, adm8691, ADM8694, adm8695 4.75 5.5 v adm8692, adm8693 4.5 5.5 v v batt operating voltage range adm8690, adm8691, ADM8694, adm8695 2.0 4.25 v adm8692, adm8693 2.0 4.0 v v out output voltage v cc C 0.005 v cc C 0.0025 v i out = 1 ma v cc C 0.2 v cc C 0.125 v i out 100 ma v out in battery backup mode v batt C 0.005 v batt C 0.002 v i out = 250 m a, v cc < v batt C 0.2 v supply current (excludes i out ) 140 200 m ai out = 100 m a supply current in battery backup mode 0.4 1 m av cc = 0 v, v batt = 2.8 v battery standby current 5.5 v > v cc > v batt + 0.2 v (+ = discharge, C = charge) C0.1 +0.02 m at a = +25 c battery switchover threshold 70 mv power-up v cc C v batt 50 mv power-down battery switchover hysteresis 20 mv batt on output voltage 0.3 v i sink = 3.2 ma batt on output short circuit current 55 ma batt on = v out = 4.5 v sink current 0.5 2.5 25 m a batt on = 0 v source current reset and watchdog timer reset voltage threshold adm8690, adm8691, ADM8694, adm8695 4.5 4.65 4.73 v adm8692, adm8693 4.25 4.4 4.48 v reset threshold hysteresis 40 mv reset timeout delay adm8690, adm8691, adm8692, adm8693 35 50 70 ms osc sel = high ADM8694, adm8695 140 200 280 ms osc sel = high watchdog timeout period, internal oscillator 1.0 1.6 2.25 s long period 70 100 140 ms short period watchdog timeout period, external clock 3840 4064 4097 cycles long period 768 1011 1025 cycles short period minimum wdi input pulse width 50 ns v il = 0.4, v ih = 3.5 v reset output voltage @ v cc = +1 v 4 20 mv i sink = 10 m a, v cc = 1 v reset , low line output voltage 0.05 0.4 v i sink = 1.6 ma, v cc = 4.25 v 3.5 v i source = 1 m a reset , wdo output voltage 0.4 v i sink = 1.6 ma 3.5 v i source = 1 m a output short circuit source current 1 10 25 m a output short circuit sink current 25 ma wdi input threshold note 1 logic low 0.8 v logic high 3.5 v wdi input current 1 10 m a wdi = v out C10 C1 m a wdi = 0 v power fail detector pfi input threshold 1.25 1.3 1.35 v v cc = +5 v pfi input current C25 0.01 +25 na pfo output voltage 0.4 v i sink = 3.2 ma 3.5 v i source = 1 m a pfo short circuit source current 1 3 25 m a pfi = low, pfo = 0 v pfo short circuit sink current 25 ma pfi = high, pfo = v out chip enable gating ce in threshold 0.8 v v il 3.0 v v ih ce in pull-up current 3 m a ce out output voltage 0.4 v i sink = 3.2 ma v out C 1.5 v i source = 3.0 ma v out C 0.05 v i source = 1 m a, v cc = 0 v ce propagation delay 3 7 ns rev. 0 C2C (v cc = full operating range, v batt = +2.8 v, t a = t min to t max unless otherwise noted)
parameter min typ max units test conditions/comments oscillator osc in input current 2 m a osc sel input pull-up current 5 m a osc in frequency range 0 500 khz osc sel = 0 v osc in frequency with external capacitor 4 khz osc sel = 0 v, c osc = 47 pf note 1 wdi is a three level input which is internally biased to 38% of v cc and has an input impedance of approximately 5 m w . specifications subject to change without notice. adm8690Cadm8695 rev. 0 C3C absolute maximum ratings* (t a = +25 c unless otherwise noted) v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v v batt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +6 v all other inputs . . . . . . . . . . . . . . . . . . C0.3 v to v out + 0.5 v input current v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 ma v batt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma digital output current . . . . . . . . . . . . . . . . . . . . . . . . . 20 ma power dissipation, n-8 dip . . . . . . . . . . . . . . . . . . . . 400 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 120 c/w power dissipation, n-16 dip . . . . . . . . . . . . . . . . . . . 600 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 135 c/w power dissipation, ru-16 dip . . . . . . . . . . . . . . . . . . 600 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 158 c/w power dissipation, r-16 soic . . . . . . . . . . . . . . . . . . 600 mw q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 110 c/w operating temperature range industrial (a version) . . . . . . . . . . . . . . . . . C40 c to +85 c extended (s version) . . . . . . . . . . . . . . . . . C55 c to +125 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . . +300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220 c storage temperature range . . . . . . . . . . . . . C65 c to +150 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods of time may affect device reliability. ordering guide model temperature range package options* adm8690an C40 c to +85 c n-8 adm8690arn C40 c to +85 c so-8 adm8691an C40 c to +85 c n-16 adm8691arn C40 c to +85 c r-16a adm8691arw C40 c to +85 c r-16 adm8691aru C40 c to +85 c ru-16 adm8692an C40 c to +85 c n-8 adm8692arn C40 c to +85 c so-8 adm8693an C40 c to +85 c n-16 adm8693arn C40 c to +85 c r-16a adm8693arw C40 c to +85 c r-16 adm8693aru C40 c to +85 c ru-16 ADM8694an C40 c to +85 c n-8 ADM8694arn C40 c to +85 c so-8 adm8695an C40 c to +85 c n-16 adm8695arw C40 c to +85 c r-16 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the adm8690Cadm8695 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. *n = plastic dip; r = small outline (wide); r = small outline (narrow); ru = thin shrink small outline; so = small outline.
adm8690Cadm8695 rev. 0 C4C pin function description mnemonic function v cc power supply input: +5 v nominal. v batt backup battery input. v out output voltage, v cc or v batt is internally switched to v out depending on which is at the highest potential. v out can supply up to 100 ma to power cmos ram. connect v out to v cc if v out and v batt are not used. gnd 0 v. ground reference for all signals. reset logic output. reset goes low if 1. v cc falls below the reset threshold 2. the watchdog timer is not serviced within its timeout period. the reset threshold is typically 4.65 v for the adm8690/adm8691/ADM8694/adm8695 and 4.4 v for the adm8692 and adm8 693. reset remains low for 50 ms (adm8690/adm8691/adm8692/ad m8693) or 200 ms (ADM8694/ adm8695) after v cc returns above the threshold. reset also goes low for 50 (200) ms if the watchdog timer is enabled but not serviced within its timeout period. the reset pulse width can be adjusted on the adm8691/adm8693/ adm8695 as shown in table i. the reset output has an internal 3 m a pull up, and can either connect to an open collector reset bus or directly drive a cmos gate without an external pull-up resistor. wdi watchdog input. wdi is a three level input. if wdi remains either high or low for longer than the watchdog timeout period, reset pulses low and wdo goes low. the timer resets with each transition on the wdi line. the watchdog timer may be disabled if wdi is left floating or is driven to midsupply. pfi power fail input. pfi is the noninverting input to the power fail comparator when pfi is less than 1.3 v, pfo goes low. connect pfi to gnd or v out when not used. pfo power fail output. pfo is the output of the power fail comparator. it goes low when pfi is less than 1.3 v. the comparator is turned off and pfo goes low when v cc is below v batt . ce in logic input. the input to the ce gating circuit. connect to gnd or v out if not used. ce out logic output. ce out is a gated version of the ce in signal. ce out tracks ce in when v cc is above the reset threshold. if v cc is below the reset threshold, ce out is forced high. see figures 5 and 6. batt on logic output. batt on goes high when v out is internally switched to the v batt input. it goes low when v out is internally switched to v cc . the output typically sinks 35 ma and can directly drive the base of an external pnp transistor to increase the output current above the 100 ma rating of v out . low line logic output. low line goes low when v cc falls below the reset threshold. it returns high as soon as v cc rises above the reset threshold. reset logic output. reset is an active high output. it is the inverse of reset . osc sel logic oscillator select input. when osc sel is unconnected (floating) or driven high, the internal oscillator sets the reset active time and watchdog timeout period. when osc sel is low, the external oscillator input, osc in, is enabled. osc sel has a 3 m a internal pull-up (see table i). osc in oscillator logic input. with osc sel low, osc in can be driven by an external clock signal or an external capacitor can be connected between osc in and gnd. this sets both the reset active pulse timing and the watch- dog timeout period (see table i and figure 4). with osc sel high or floating, the internal oscillator is enabled and the reset active time is fixed at 50 ms typ. (adm8691/adm8693) or 200 ms typ (adm8695). in this mode the osc in pin selects between fast (100 ms) and slow (1.6 s) watchdog timeout periods. in both modes, the timeout period immediately after a reset is 1.6 s typical. wdo logic output. the watchdog output, wdo , goes low if wdi remains either high or low for longer than the watchdog timeout period. wdo is set high by the next transition at wdi. if wdi is unconnected or at midsupply, the watchdog timer is disabled and wdo remains high. wdo also goes high when low line goes low.
adm8690Cadm8695 rev. 0 C5C pin configurations 1 2 3 4 8 7 6 5 top view (not to scale) adm8690 adm8692 ADM8694 v out pfo wdi reset v batt v cc gnd pfi 14 13 12 11 16 15 10 9 8 1 2 3 4 7 6 5 top view (not to scale) adm8691 adm8693 adm8695 v batt ce in wdo reset reset v out v cc gnd pfo wdi ce out batt on low line osc in osc sel pfi circuit information battery switchover section the battery switchover circuit compares v cc to the v batt input, and connects v out to whichever is higher. switchover occurs when v cc is 50 mv higher than v batt as v cc falls, and when v cc is 70 mv greater than v batt as v cc rises. this 20 mv of hysteresis prevents repeated rapid switching if v cc falls very slowly or remains nearly equal to the battery voltage. v cc v batt v out batt on (adm8690, adm8695) 100 mv 700 mv internal shutdown signal when v batt > (v cc + 0.7v) gate drive figure 1. battery switchover schematic during normal operation, with v cc higher than v batt , v cc is internally switched to v out via an internal pmos transistor switch. this switch has a typical on-resistance of 0.7 w and can supply up to 100 ma at the v out terminal. v out is normally used to drive a ram memory bank which may require instanta- neous currents of greater than 100 ma. if this is the case then a bypass capacitor should be connected to v out . the capacitor will provide the peak current transients to the ram. a capaci- tance value of 0.1 m f or greater may be used. if the continuous output current requirement at v out exceeds 100 ma, or if a lower v cc Cv out voltage differential is desired, an external pnp pass transistor may be connected in parallel with the internal transistor. the batt on output (adm8691/ adm8693/adm8695) can directly drive the base of the exter- nal transistor. a 7 w mosfet switch connects the v batt input to v out dur- ing battery backup. this mosfet has very low input-to-out- put differential (dropout voltage) at the low current levels required for battery back up of cmos ram or other low power cmos circuitry. the supply current in battery back up is typi- cally 0.4 m a. the adm8690/adm8691/ADM8694/adm8695 operates with battery voltages from 2.0 v to 4.25 v, and the adm8692/ adm8693 operates with battery voltages from 2.0 v to 4.0 v. high value capacitors, either standard electrolytic or the farad size double layer capacitors, can also be used for short-term memory backup. a small charging current of typically 10 na (0.1 m a max) flows out of the v batt terminal. this current is useful for maintaining rechargeable batteries in a fully charged condition. this extends the life of the backup battery by com- pensating for its self discharge current. also note that this cur- rent poses no problem when lithium batteries are used for backup since the maximum charging current (0.1 m a) is safe for even the smallest lithium cells. if the battery switchover section is not used, v batt should be connected to gnd and v out should be connected to v cc . product selection guide part nominal reset nominal v cc nominal watchdog battery backup base drive chip enable number time reset threshold timeout period switching ext pnp signals adm8690 50 ms 4.65 v 1.6 s yes no no adm8691 50 ms or adj 4.65 v 100 ms, 1.6 s, adj yes yes yes adm8692 50 ms 4.4 v 1.6 s yes no no adm8693 50 ms or adj 4.4 v 100 ms, 1.6 s, adj yes yes yes ADM8694 200 ms 4.65 v 1.6 s yes no no adm8695 200 ms or adj 4.65 v 100 ms, 1.6 s, adj yes yes yes
adm8690Cadm8695 rev. 0 C6C watchdog timer reset the watchdog timer circuit monitors the activity of the micro- processor in order to check that it is not stalled in an indefinite loop. an output line on the processor is used to toggle the watchdog input (wdi) line. if this line is not toggled within the selected timeout period, a reset pulse is generated. the nominal watchdog timeout period is preset at 1.6 seconds on the adm8690/adm8692/ADM8694. the adm8691/adm8693/ adm8695 may be configured for either a fixed short 100 ms or a long 1.6 second timeout period or for an adjustable timeout period. if the short period is selected, some systems may be unable to service the watchdog timer immediately after a reset, so the adm8691/adm8693/adm8695 automatically se- lects the long timeout period directly after a reset is issued. the watchdog timer is restarted at the end of reset, whether the reset was caused by lack of activity on wdi or by v cc falling be- low the reset threshold. the normal (short) timeout period becomes effective following the first transition of wdi after reset has gone inactive. the watchdog timeout period restarts with each transition on the wdi pin. to ensure that the watchdog timer does not time out, either a high-to-low or low-to-high transition on the wdi pin must occur at or less than the minimum timeout period. if wdi remains permanently either high or low, reset pulses will be issued after each long (1.6 s) timeout period. the watchdog monitor can be deactivated by floating the watchdog input (wdi) or by connecting it to midsupply. wdi wdo reset t 3 t 2 t 1 t 1 t 1 t 1 = reset time t 2 = normal (short) watchdog timeout period t 3 = watchdog timeout period immediately following a reset figure 3. watchdog timeout period and reset active time power fail reset output reset is an active low output that provides a reset signal to the microprocessor whenever v cc is at an invalid level. when v cc falls below the reset threshold, the reset output is forced low. the nominal reset voltage threshold is 4.65 v (adm8690/adm8691/ADM8694/adm8695) or 4.4 v (adm8692/ adm8693). v cc reset low line t 1 t 1 t 1 = reset time v1 = reset voltage threshold low v2 = reset voltage threshold high hysteresis = v2?1 v1 v2 v2 v1 figure 2. power fail reset timing on power-up, reset will remain low for 50 ms (200 ms for ADM8694 and adm8695) after v cc rises above the appropri- ate reset threshold. this allows time for the power supply and microprocessor to stabilize. on power-down, the reset out- put remains low with v cc as low as 1 v. this ensures that the microprocessor is held in a stable shutdown condition. this reset active time is adjustable on the adm8691/ adm8693/adm8695 by using an external oscillator or by connecting an external capacitor to the osc in p in. refer to table i and figure 4. the guaranteed minimum and maximum thresholds of the adm8690/adm8691/ADM8694/adm8695 are 4.5 v and 4.73 v, while the guaranteed thresholds of the adm8692/ adm8693 are 4.25 v and 4.48 v. the adm8690/adm8691/ ADM8694/adm8695 is, therefore, compatible with 5 v sup- plies with a +10%, C5% tolerance while the adm8692/ adm8693 is compatible with 5 v 10% supplies. the reset threshold comparator has approximately 50 mv of hysteresis. the response time of the reset voltage comparator is less than 1 m s. if glitches are present on the v cc line which could cause spurious reset pulses, then v cc should be decoupled close to the device. in addition to reset the adm8691/adm8693/adm8695 contain an active high reset output. this is the complement of reset and is intended for processors requiring an active high reset signal.
adm8690Cadm8695 rev. 0 C7C table i. adm8691, adm8693, adm8695 reset pulse width and watchdog timeout selections watchdog timeout period reset active period immediately osc sel osc in normal after reset adm8691/adm8693 adm8695 low external clock input 1024 clks 4096 clks 512 clks 2048 clks low external capacitor 400 ms c/47 pf 1.6 s c/47 pf 200 ms c/47 pf 520 ms c/47 pf floating or high low 100 ms 1.6 s 50 ms 200 ms floating or high floating or high 1.6 s 1.6 s 50 ms 200 ms note with the osc sel pin low, osc in can be driven by an external clock signal, or an external capacitor can be connected between o sc in and gnd. the nominal internal oscillator frequency is 10.24 khz. the nominal oscillator frequency with external capacitor is: f osc (hz) = 184,000/c (pf) on the adm8690/adm8692 the watchdog timeout period is fixed at 1.6 seconds and the reset pulse width is fixed at 50 ms. on the ADM8694 the watchdog timeout period is also 1.6 sec- onds but the reset pulse width is fixed at 200 ms. the a dm8691/ adm8693/adm8695 allow these times to be adjusted as shown in table i. figure 4 shows the various oscillator configu- rations that can be used to adjust the reset pulse width and watchdog timeout period. the internal oscillator is enabled when osc sel is high or floating. in this mode, osc in selects between the 1.6 second and 100 ms watchdog timeout periods. with osc in con nected high or floating, the 1.6 second timeout period is selected; while with it connected low, the 100 ms timeout period is selected. in either case, immediately after a reset the timeout period is 1.6 seconds. this gives the microprocessor time to reinitialize the system. if osc in is low, then the 100 ms watchdog period be- comes effective after the first transition of wdi. the software should be written such that the i/o port driving wdi is left in its power-up reset state until the initialization routines are com- pleted and the microprocessor is able to toggle wdi at the mini- mum watchdog timeout period of 70 ms. watchdog output (wdo) the watchdog output wdo (adm8691/adm8693/ adm8695) provides a status output which goes low if the watchdog timer times out and remains low until set high by the next transition on the watchdog input. wdo is also set high when v cc goes below the reset threshold. 8 7 clock 0 to 500khz osc sel osc in adm8691 adm8693 adm8695 figure 4a. external clock source 8 7 osc sel osc in adm8691 adm8693 adm8695 c osc figure 4b. external capacitor 8 7 nc nc osc sel osc in adm8691 adm8693 adm8695 figure 4c. internal oscillator (1.6 second watchdog) 8 7 osc sel osc in adm8691 adm8693 adm8695 nc figure 4d. internal oscillator (100 ms watchdog)
adm8690Cadm8695 rev. 0 C8C (pfi) is compared to an internal +1.3 v reference. the power fail output ( pfo ) goes low when the voltage at pfi is less than 1.3 v. typically pfi is driven by an external voltage divider that senses either the unregulated dc input to the systems 5 v regu- lator or the regulated 5 v output. the voltage divider ratio can be chosen such that the voltage at pfi falls below 1.3 v several milliseconds before the +5 v power supply falls below the reset threshold. pfo is normally used to interrupt the microprocessor so that data can be stored in ram and the shut down procedure executed before power is lost adm869x 1.3v power fail output power fail input pfo r1 r2 input power figure 7. power fail comparator table ii. input and output status in battery backup mode signal status v out v out is connected to v batt via an internal pmos switch. reset logic low. reset logic high. the open circuit output voltage is equal to v out . low line logic low. batt on logic high. the open circuit voltage is equal to v out. wdi wdi is ignored. it is internally disconnected from the internal pull-up resistor and does not source or sink current as long as its input voltage is between gnd and v out . the input voltage does not affect supply current. wdo logic high. the open circuit voltage is equal to v out . pfi the power fail comparator is turned off and has no effect on the power fail output. pfo logic low. ce in ce in is ignored. it is internally disconnected from its internal pull-up and does not source or sink current as long as its input voltage is between gnd and v out . the input voltage does not affect supply current. ce out logic high. the open circuit voltage is equal to v out . osc in osc in is ignored. osc sel osc sel is ignored. ce gating and ram write protection (adm8691/adm8693/ adm8695) the adm8691/adm8693/adm8695 products include memory protection circuitry which ensures the integrity of data in memory by preventing write operations when v cc is at an in- valid level. there are two additional pins, ce in and ce out , which may be used to control the chip enable or write inputs of cmos ram. when v cc is present, ce out is a buffered rep- lica of ce in , with a 3 ns propagation delay. when v cc falls be- low the reset voltage threshold or v batt , an internal gate forces ce out high, independent of ce in . ce out typically drives the ce , cs or write input of battery backed up cmos ram. this ensures the integrity of the data in memory by preventing write operations when v cc is at an in- valid level. similar protection of eeproms can be achieved by using the ce out to drive the store or write inputs. adm869x ce in ce out v cc low = 0 v cc ok = 1 figure 5. chip enable gating v cc reset low line t 1 t 1 t 1 = reset time v1 = reset voltage threshold low v2 = reset voltage threshold high hysteresis = v2?1 v1 v2 v2 v1 ce in ce out figure 6. chip enable timing power fail warning comparator an additional comparator is provided for early warning of fail- ure in the microprocessors power supply. the power fail input
typical performance curvesCadm8690Cadm8695 rev. 0 C9C i out ?ma 5.00 20 100 40 60 80 v out ?volts 4.94 10 30 50 70 90 4.99 4.98 4.97 4.96 4.95 figure 8. v out vs. i out normal operation temperature ? c 1.315 1.295 1.28 ?0 ?0 120 030 90 1.29 1.285 pfi input threshold ?volts 60 1.31 1.305 1.3 figure 11. pfi input threshold vs. temperature time ?? 6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 5 0 1.35 1.25 2 1 4 3 v cc = 5v t a = +25 c pfo v pfi 1.3v 30pf figure 14. power fail comparator response time i out ?? 2.8 1050 2.786 150 250 350 450 550 650 750 850 950 2.798 2.794 2.792 2.79 2.788 2.796 v out ?volts figure 9. v out vs. i out battery backup temperature ? c 53 52 49 20 40 120 60 80 100 51 50 reset active time ?ms v cc = +5v adm8690 adm8691 adm8692 adm8693 figure 12. reset active time vs. temperature time ?? 6 0 10 20 30 40 50 60 70 80 5 0 1.35 1.25 2 1 4 3 v cc = 5v t a = +25 c pfo v pfi 1.3v 30pf 90 figure 15. power fail comparator response time 10 90 100 0% 3.36 v 500ms a4 1v 1v figure 10. reset output voltage vs supply voltage temperature ? c 4.69 4.67 4.55 ?0 ?0 120 30 60 90 4.65 4.63 reset voltage threshold ?v v cc = +5v 4.61 4.59 4.57 0 figure 13. reset voltage threshold vs. temperature time ?? 6 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 5 0 1.35 1.25 2 1 4 3 v cc = 5v t a = +25 c pfo v pfi 1.3v 30pf 10k w +5v 1.8 figure 16. power fail comparator response time with pull-up resistor
adm8690Cadm8695 rev. 0 C10C +application information increasing the drive current if the continuous output current requirements at v out exceed 100 ma, or if a lower v cc Cv out voltage differential is desired, an external pnp pass transistor may be connected in parallel with the internal transistor. the batt on output (adm8691/ adm8693/adm8695) can directly drive the base of the exter- nal transistor. pnp transistor 0.1? 0.1? battery +5v input power v cc batt on v out v batt adm8691 adm8693 adm8695 figure 17. increasing the drive current using a rechargeable battery for backup if a capacitor or a rechargeable battery is used for backup then the charging resistor should be connected to v out since this eliminates the discharge path that would exist during power- down if the resistor is connected to v cc . 0.1? 0.1? rechargeable battery +5v input power v cc v out v batt adm869x r i = v out ?v batt r figure 18. rechargeable battery adding hysteresis to the power fail comparator for increased noise immunity, hysteresis may be added to the power fail comparator. since the comparator circuit is nonin- verting, hysteresis can be added simply by connecting a resistor be- tween the pfo output and the pfi input as shown in figure 19. when pfo is low, resistor r 3 sinks current from the summing junction at the pfi pin. when pfo is high, the series combina- tion of r3 and r4 source current into the pfi summing junc- tion. this results in differing trip levels for the comparator. adm869x 1.3v pfi pfo r 1 r 2 +7v to +15v input power r 4 r 3 v cc to ? nmi +5v 7805 5v 0v pfo 0v v l v h v in v h = 1.3v ( 1+ + ) v l = 1.3v ( 1+ ? ) assuming r 4 < < r 3 then r 1 r 2 r 1 r 3 r 1 r 2 r 1 (5v ?1.3v) 1.3v (r 3 + r 4 ) r 1 r 2 hysteresis v h ?v l = 5v ( ) figure 19. adding hysteresis to the power fail comparator monitoring the status of the battery the power fail comparator can be used to monitor the status of the backup battery instead of the power supply if desired. this is shown in figure 20. the pfi input samples the battery volt- age and generates an active low pfo signal when the battery voltage drops below a chosen threshold. it may be necessary to apply a test load in order to determine the loaded battery volt- age. this can be done under processor control using ce out. since ce out is forced high during the battery backup mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered. adm869x pfo +5v input power ce in ce out pfi v batt v cc battery 20k w optional test load 10m w 10m w low battery signal to ? i/o pin from ? i/o pin applies test load to battery figure 20. monitoring the battery status alternate watchdog input drive circuits the watchdog feature can be enabled and disabled under pro- gram control by driving wdi with a three-state buffer (figure 21a). when three-stated, the wdi input will float, thereby dis- abling the watchdog timer. wdi adm869x watchdog strobe control input figure 21a. programming the watchdog input this circuit is not entirely foolproof, and it is possible that a software fault could erroneously three-state the buffer. this would then prevent the adm869x from detecting that the mi- croprocessor is no lon ger operating correctly. in most cases a better method is to extend the watchdog period rather than dis- abling the watchdog. this may be done under program control using the circuit shown in figure 21b. when the control input is high, the osc sel pin is low and the watchdog timeout is set by the external capacitor. a 0.01 m f capacitor sets a watchdog timeout delay of 100 seconds. when the control input is low, the osc sel pin is driven high, selecting the internal oscillator. the 100 ms or the 1.6 s period is chosen, depending on which di- ode in figure 21b is used. with d1 inserted, the internal timeout is set at 100 ms; with d2 inserted the timeout is set at 1.6 s. d2 d1 control input* adm869x osc sel osc in *low = internal timeout high = external timeout figure 21b. programming the watchdog input
adm8690Cadm8695 rev. 0 C11C typical applications adm8690, adm8692 and ADM8694 figure 22a shows the adm8690/adm8692/ADM8694 in a typical power monitoring, battery backup application. v out powers the cmos ram. under normal operating conditions with v cc present, v out is internally connected to v cc . if a power failure occurs, v cc will decay and v out will be switched to v batt thereby maintaining power for the cmos ram. a reset pulse is also generated when v cc falls below 4.65 v for the adm8690/ADM8694 or 4.4 v for the adm8692. reset will remain low for 50 ms (200 ms for ADM8694) after v cc re- turns to 5 v. the watchdog timer input (wdi) monitors an i/o line from the m p system. this line must be toggled once every 1.6 seconds to verify correct software execution. failure to toggle the line indi- cates that the m p system is not correctly executing its program and may be tied up in an endless loop. if this happens, a reset pulse is generated to initialize the processor. if the watchdog timer is not needed, the wdi input should be left floating. the power fail input, pfi, monitors the input power supply via a resistive divider network. the voltage on the pfi input is com- pared with a precision 1.3 v internal reference. if the input volt- age drops below 1.3 v, a power fail output ( pfo ) signal is generated. this warns of an impending power failure and may be used to interrupt the processor so that the system may be shut down in an orderly fashion. the resistors in the sensing network are ratioed to give the desired power fail threshold voltage v t . v t = (1.3 r 1/ r 2) + 1.3 v r 1/ r 2 = ( v t /1.3) C 1 + battery r 1 r 2 +5v 0.1? adm8690 adm8692 ADM8694 v cc pfi v batt v out wdi pfo reset gnd ? power cmos ram power ? system ? reset ? nmi i/o line figure 22a. a dm8690/adm8692/ADM8694 typical applica- tion circuit a figure 22b shows a similar application but in this case the pfi input monitors the unregulated input to the 7805 voltage regu- lator. this gives an earlier warning of an impending power fail- ure. it is useful with processors operating at low speeds or where there are a significant number of housekeeping tasks to be com- pleted before the power is lost. + battery r 1 r 2 input power v > 8v 0.1? 0.1? 7805 +5v ? power cmos ram power ? system ? reset ? nmi i/o line adm8690 adm8692 ADM8694 v cc pfi v batt v out wdi pfo reset gnd figure 22b. a dm8690/adm8692/ADM8694 typical applica- tion circuit b adm8691, adm8693 and adm8695 a typical connection for the adm8691/adm8693/adm8695 is shown in figure 23. cmos ram is powered from v out . when 5 v power is present this is routed to v out . if v cc fails then v batt is routed to v out . v out can supply up to 100 ma from v cc , but if more current is required, an external pnp tran- sistor can be added. when v cc is higher than v batt , the batt on output goes low, providing up to 25 ma of base drive for the external transistor. a 0.1 m f capacitor is connected to v out to supply the transient currents for cmos ram. when v cc is lower than v batt , an internal 20 w mosfet connects the backup battery to v out . 3v battery r 1 r 2 0.1? 0.1? 0.1? reset system status indicators nc input power +5v a0?15 i/o line nmi reset ? adm8691 adm8693 adm8695 batt on v cc v out v batt ce out ce in pfi gnd osc in osc sel wdi pfo reset low line wdo address decode cmos ram figure 23. adm8691/adm8693/adm8695 typical application
adm8690Cadm8695 rev. 0 C12C reset output the internal voltage detector monitors v cc and generates a reset output to hold the microprocessors reset line low when v cc is below 4.65 v (4.4 v for adm8693). an internal timer holds reset low for 50 ms (200 ms for the adm8695) after v cc rises above 4.65 v (4.4 v for adm8693). this pre- vents repeated toggling of reset even if the 5 v power drops out and recovers with each power line cycle. the crystal oscillator normally used to generate the clock for microprocessors can take several milliseconds to stabilize. since most microprocessors need several clock cycles to reset, reset must be held low until the microprocessor clock oscillator has started. the power-up reset pulse lasts 50 ms (200 ms for the adm8695) to allow for this oscillator start-up time. if a differ- ent reset pulse width is required, then a capacitor should be connected to osc in or an external clock may be used. please refer to table i and figure 4. the manual reset switch and the 0.1 m f capacitor connected to the reset line can be omitted if a manual reset is not needed. an inverted, active high, reset output is also available. power fail detector the +5 v v cc power line is monitored via a resistive potential divider connected to the power fail input (pfi). when the voltage at pfi falls below 1.3 v, the power fail output ( pfo ) drives the processors nmi input low. if for example a power fail threshold of 4.8 v is set with resistors r 1 and r 2 , the micro- processor will have the time when v cc falls from 4.8 v to 4.65 v to save data i nto ram. an earlier power fail warning can be gen- erated if the unregulated dc input to the 5 v regulator is avail- able for monitoring. this will allow more time for micro- processor housekeep ing tasks to be completed before power is lost. ram write protection the adm8691/adm8693/adm8695 ce out line drives the chip select inputs of the cmos ram. ce out follows ce in as long as v cc is above the 4.65 v (4.4 v for adm8693) reset threshold. if v cc falls below the reset threshold, ce out goes high, inde- pendent of the logic level at ce in . this prevents the micropro- cessor from writing erroneous data into ram during power-up, power-down, brownouts and momentary power interruptions. watchdog timer the microprocessor drives the watchdog input (wdi) with an i/o line. when osc in and osc sel are unconnected, the microprocessor must toggle the wdi pin once every 1.6 seconds to verify proper software execution. if a hardware or software failure occurs such that wdi is not toggled, the adm8691/ adm8693 will issue a 50 ms (200 ms for adm8695) reset pulse after 1.6 seconds. this typically restarts the micro- processors power-up routine. a new reset pulse is issued every 1.6 seconds until wdi is again strobed. if a different watchdog timeout period is required, then a capacitor should be connected to osc in or an external clock may be used. please refer to table i and figure 4. the watchdog output ( wdo ) goes low if the watchdog timer is not serviced within its timeout period. once wdo goes low, it remains low until a transition occurs at wdi. the w atchdog timer feature can be disabled by leaving wdi unconnected. the reset output has an internal 3 m a pull-up, and can either connect to an open collector reset bus or directly drive a cmos gate without an external pull-up resistor.
adm8690Cadm8695 rev. 0 C13C outline dimensions dimensions shown in inches and (mm). 8-pin plastic dip (n-8) 8 14 5 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) max 0.150 (3.81) min 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.160 (4.06) 0.115 (2.93) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93) 16-lead plastic dip (n-16) 16 18 9 0.840 (21.33) 0.745 (18.93) 0.280 (7.11) 0.240 (6.10) pin 1 seating plane 0.022 (0.558) 0.014 (0.356) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) 0.150 (3.81) 0.070 (1.77) 0.045 (1.15) 0.100 (2.54) bsc 0.200 (5.05) 0.125 (3.18) 0.325 (8.25) 0.300 (7.62) 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93)
adm8690Cadm8695 rev. 0 C14C 8-lead small outline (so-8) 0.1968 (5.00) 0.1890 (4.80) 8 5 4 1 0.2440 (6.20) 0.2284 (5.80) pin 1 0.1574 (4.00) 0.1497 (3.80) 0.0688 (1.75) 0.0532 (1.35) seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45 16-lead small outline (wide body) (r-16) 16 9 8 1 pin 1 0.413 (10.50) 0.419 (10.65) 0.299 (7.60) seating plane 0.05 (1.27) bsc 0.104 (2.65) 0.019 (0.49) 0.012 (0.3) 0.013 (0.32) 0.042 (1.07) 0.030 (0.75) 16-lead small outline (narrow body) (r-16a) 16 9 8 1 0.3937 (10.00) 0.3859 (9.80) 0.2550 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (5.80) pin 1 seating plane 0.0098 (0.25) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.0688 (1.75) 0.0532 (1.35) 0.0500 (1.27) bsc 0.0099 (0.25) 0.0075 (0.19) 0.0500 (1.27) 0.0160 (0.41) 8 0 0.0196 (0.50) 0.0099 (0.25) x 45
adm8690Cadm8695 rev. 0 C15C 16-lead thin shrink small outline (ru-16) 16 9 8 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0
c2932C10C2/97 printed in u.s.a. C16C

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